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74LVT322245 * 74LVTH322245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs
May 2002 Revised May 2002
74LVT322245 * 74LVTH322245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs
General Description
The LVT322245 and LVTH322245 contain thirty-two noninverting bidirectional buffers with 3-STATE outputs and are intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 32-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVT322245 and LVTH322245 are designed with equivalent 25 series resistance in both the HIGH and LOW states on the A Port outputs. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH322245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT322245 and LVTH322245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH322245) s Also available without bushold feature (74LVT322245) s Live insertion/extraction permitted s Power Up/Power Down high impedance provides glitch-free bus loading s A Port outputs include equivalent series resistance of 25 making external termination resistors unnecessary and reducing overshoot and undershoot s A Port outputs source/sink 12 mA B Port outputs source/sink -32 mA/+64 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT322245G (Note 1) (Note 2) 74LVTH322245G (Note 1) (Note 2) Package Number BGA96A (Preliminary) BGA96A Package Description 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 1: Ordering code "G" indicates TRAYS. Note 2: Devices also available in TAPE and REEL. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbol
(c) 2002 Fairchild Semiconductor Corporation
DS500408
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74LVT322245 * 74LVTH322245
Connection Diagram
FBGA Pin Descriptions
Pin Names OEn T/Rn A0-A31 B0-B31 Description Output Enable Input (Active LOW) Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs
Pin Assignments for FBGA
1 A B C D E F G H (Top Thru View) J K L M N P R T B1 B3 B5 B7 B9 B11 B13 B14 B17 B19 B21 B23 B25 B27 B29 B30 2 B0 B2 B4 B6 B8 B10 B12 B15 B16 B18 B20 B22 B24 B26 B28 B31 3 T/R1 GND VCC1 GND GND VCC1 GND T/R2 T/R3 GND VCC2 GND GND VCC2 GND T/R4 4 OE1 GND VCC1 GND GND VCC1 GND OE2 OE3 GND VCC2 GND GND VCC2 GND OE4 5 A0 A2 A4 A6 A8 A10 A12 A15 A16 A18 A20 A22 A24 A26 A28 A31 6 A1 A3 A5 A7 A9 A11 A13 A14 A17 A19 A21 A23 A25 A27 A29 A30
Truth Tables
Inputs OE1 L L H Inputs OE2 L L H T/R2 L H X Outputs Bus B8-B15 Data to Bus A8-A15 Bus A8-A15 Data to Bus B8-B15 HIGH-Z State on A8-A15, B8-B15 T/R1 L H X Outputs Bus B0-B7 Data to Bus A0-A7 Bus A0-A7 Data to Bus B0-B7 HIGH-Z State on A0-A7, B0-B7 Inputs OE3 L L H Inputs OE4 L L H T/R4 L H X Outputs Bus B24-B31 Data to Bus A24-A31 Bus A24-A31 Data to Bus B24-B31 HIGH-Z State on A24-A31, B24-B31 T/R3 L H X Outputs Bus B16-B23 Data to Bus A16-A23 Bus A16-A23 Data to Bus B16-B23 HIGH-Z State on A16-A23, B16-B23
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance
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74LVT322245 * 74LVTH322245
Functional Description
The LVT322245 and LVTH322245 contain thirty-two non-inverting bidirectional buffers with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain 16-bit or full 32-bit operation.
Logic Diagrams
Byte 1 Byte 3
Byte 2
Byte 4
VCC1 is associated with Bytes 1 and 2. VCC2 is associated with Bytes 3 and 4.
Note: Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74LVT322245 * 74LVTH322245
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI < GND VO < GND VO > VCC VO > VCC Output at HIGH State Output at LOW State V mA mA mA mA mA
-0.5 to +4.6 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -50 -50
64 128
64 128 -65 to +150
C
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature Input Edge Rate, VIN = 0.8V-2.0V, VCC = 3.0V B Port A Port B Port A Port Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
-32 -12
64 12
-40
0
+85
10
C
ns/V
t/V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage A Port B Port VOL Output LOW Voltage A Port VCC (V) 2.7 2.7-3.6 2.7-3.6 3.0 2.7-3.6 2.7 3.0 3.0 2.7 2.7 B Port 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF Power Off Leakage Current 3.6 3.6 3.6 0 Bushold Input Minimum Drive 3.0 3.0 75 -75 500 -500 10 1 -5 1 100 A A 2.0 VCC- 0.2 2.4 2.0 0.8 0.2 0.5 0.4 0.5 0.55 A A V 2.0 0.8 TA = -40C to +85C Min Max -1.2 Units V V V V V V V V Conditions II = -18 mA VO 0.1V or VO VCC - 0.1V IOH = -12 mA IOH = -100 A IOH = -8 mA IOH = -32 mA IOL = 12 mA IOL = 100 A IOL = 24 mA IOL = 16 mA IOL = 32 mA IOL = 64 mA VI = 0.8V VI = 2.0V (Note 6) (Note 7) VI = 5.5V VI = 0V or VCC VI = 0V VI = VCC 0V VI or VO 5.5V
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74LVT322245 * 74LVTH322245
DC Electrical Characteristics
Symbol IPU/PD IOZL IOZL (Note 5) IOZH IOZH (Note 5) IOZH+ ICCH ICCL ICCZ ICCZ+ ICC Power Up/Down 3-STATE Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 8) Parameter
(Continued)
VCC (V) 0-1.5V 3.6 3.6 3.6 3.6 3.6 TA = -40C to +85C Min Max 100 -5 -5 5 5 10 0.19 5 0.19 0.19 0.2 A A A A A A mA mA mA mA mA VO = 0.5V to 3.0V VI = GND to VCC VO = 0.5V VO = 0.0V VO = 3.0V VO = 3.6V VCC < VO 5.5V Outputs HIGH Outputs LOW Outputs Disabled VCC VO 5.5V, Outputs Disabled One Input at VCC - 0.6V Other Inputs at VCC or GND
Units
Conditions
VCC1 or VCC2 VCC1 or VCC2 VCC1 or VCC2 VCC1 or VCC2
3.6 3.6 3.6 3.6 3.6
VCC1 or VCC2
Note 5: Applies to bushold versions only (74LVTH322245). Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 9)
TA = 25C Min Typ 0.8 -0.8 Max Units V V Conditions CL = 50 pF RL = 500 (Note 10) (Note 10)
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n-1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA = -40C to +85C Symbol Parameter CL = 50 pF, RL = 500 VCC = 3.3V 0.3V Min tPLH tPHL tPLH tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ Output Disable Time for B Port Output Output Disable Time for A Port Output Output Enable Time for B Port Output Output Enable Time for A Port Output Propagation Delay Data to B Port Output Propagation Delay Data to A Port Output 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5 Max 4.0 3.7 3.5 3.5 5.3 5.6 4.6 5.3 5.6 5.5 5.4 5.1 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5 VCC = 2.7V Min Max 4.6 4.1 3.9 3.9 6.3 7.2 5.4 6.9 6.3 5.5 6.1 5.4 ns ns ns ns ns ns Units
Capacitance
Symbol CIN CI/O
(Note 11)
Parameter Conditions VCC = 0V, VI = 0V or VCC VCC = 3.0V, VO = 0V or VCC Typical 4 8 Units pF pF
Input Capacitance Input/Output Capacitance
Note 11: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.
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74LVT322245 * 74LVTH322245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA96A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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